In recent years, nonvolatile semiconductor storage devices such as flash memory have been used increasingly in a variety of electronic products. Writing data to such a nonvolatile semiconductor storage device is done in blocks of multiple bits or on a bit-by-bit basis.
More specifically, data is written to the nonvolatile semiconductor storage device by applying, for example, a voltage of about 5 V via the bit line; here, the maximum number of bits that may be written simultaneously (maximum simultaneously writable bit number) depends on the capability of the power supply circuit that generates the 5-V power.
Besides, between a 1-bit write operation in which one bit is written at a time and a 4-bit write operation in which four bits are written at a time, for example, there is a gap in the margin to be allowed for the capability of the power supply circuit.
When programming, there will be no problem as long as the write voltage applied to each memory cell is greater than a given threshold voltage but, when performing erasure thereafter, if the threshold voltage varies between memory cells, it will adversely affect the number of erasures.
In the related art, when writing data in blocks of multiple bits, if, for example, a fraction (remainder) is left after writing the multiple bits, the remaining bits representing the fraction are written at the end of the write process.
More specifically, when the maximum simultaneously writable bit number is 4, the data is first written in sequence in blocks of four bits, and then the remaining bits, if any, are written at the end of the write process.
That is, when the number of remaining bits is 3, these three bits are written at the end of the write process, likewise, when the number of remaining bits is 2, these two bits are written, and when the number of remaining bits is 1, this one bit is written.
However, when writing data in blocks of multiple bits, if the number of bits to be written simultaneously differs between write operations, the load applied to the power supply circuit varies. As a result, when performing erasure after programming, for example, the threshold voltage varies between memory cells, causing an ill effect on the number of erasures.
In an alternative design, the capacity of the power supply circuit (or the power supply section of the nonvolatile semiconductor storage device (memory macro)) has been increased to provide a greater margin in order to suppress the variation of the threshold voltage between memory cells.
In the related art, various designs have been proposed for nonvolatile semiconductor storage devices that perform simultaneous writing by controlling write pulses using a counter.    Patent Document 1: Japanese Laid-open Patent Publication No. 2006-085896    Patent Document 2: Japanese Laid-open Patent Publication No. 2002-109894    Patent Document 3: Japanese Laid-open Patent Publication No. H07-122088